-; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
-; Check that we generate conversion from double precision floating point
-; to 32-bit int value in IEEE rounding to the nearest mode in V5.
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; CHECK: __hexagon_addsf3
+; CHECK: __hexagon_subsf3
-; CHECK: r{{[0-9]+}} = convert_sf2w(r{{[0-9]+}})
-
-define i32 @main() nounwind {
+define void @foo(float* %acc, float %num, float %num2) nounwind {
entry:
- %retval = alloca i32, align 4
- %i = alloca i32, align 4
- %a = alloca float, align 4
- %b = alloca float, align 4
- %c = alloca float, align 4
- store i32 0, i32* %retval
- store float 0x402ECCCCC0000000, float* %a, align 4
- store float 0x4022333340000000, float* %b, align 4
- %0 = load float* %a, align 4
- %1 = load float* %b, align 4
- %add = fadd float %0, %1
- store float %add, float* %c, align 4
- %2 = load float* %c, align 4
- %conv = fptosi float %2 to i32
- store i32 %conv, i32* %i, align 4
- %3 = load i32* %i, align 4
- ret i32 %3
+ %acc.addr = alloca float*, align 4
+ %num.addr = alloca float, align 4
+ %num2.addr = alloca float, align 4
+ store float* %acc, float** %acc.addr, align 4
+ store float %num, float* %num.addr, align 4
+ store float %num2, float* %num2.addr, align 4
+ %0 = load float** %acc.addr, align 4
+ %1 = load float* %0
+ %2 = load float* %num.addr, align 4
+ %add = fadd float %1, %2
+ %3 = load float* %num2.addr, align 4
+ %sub = fsub float %add, %3
+ %4 = load float** %acc.addr, align 4
+ store float %sub, float* %4
+ ret void
}