R600: Implement zero undef variants of ctlz/cttz

[oota-llvm.git] / test / CodeGen / Hexagon / opt-fneg.ll

diff --git a/test/CodeGen/Hexagon/opt-fneg.ll b/test/CodeGen/Hexagon/opt-fneg.ll
index cf7e2d571df7482e46d9e7bc541c85b7498873bb..479b4b64069a8d14107f9ab10853133970605423 100644 (file)
--- a/test/CodeGen/Hexagon/opt-fneg.ll
+++ b/test/CodeGen/Hexagon/opt-fneg.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv5  < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
 ; Optimize fneg to togglebit in V5.
 
-define float @bar(float %x) nounwind {
+define float @foo(float %x) nounwind {
 entry:
 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
   %x.addr = alloca float, align 4
@@ -11,14 +11,16 @@ entry:
   ret float %sub
 }
 
+define float @bar(float %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+  %sub = fsub float -0.000000e+00, %x
+  ret float %sub
+}
+
 define float @baz(float %x) nounwind {
 entry:
 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
-  %x.addr = alloca float, align 4
-  store float %x, float* %x.addr, align 4
-  %0 = load float* %x.addr, align 4
-  %conv = fpext float %0 to double
-  %mul = fmul double %conv, -1.000000e+00
-  %conv1 = fptrunc double %mul to float
+  %conv1 = fmul float %x, -1.000000e+00
   ret float %conv1
 }