AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsics

[oota-llvm.git] / test / CodeGen / MSP430 / AddrMode-bis-rx.ll

diff --git a/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
index c7ecb5ab853f8798dc4082bf9422261d58a7a8a5..44c92ebc82cc0b1858ea64e58034ad14bdcb5a59 100644 (file)
--- a/test/CodeGen/MSP430/AddrMode-bis-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -7,7 +7,7 @@ define i16 @am1(i16 %x, i16* %a) nounwind {
        %2 = or i16 %1,%x
        ret i16 %2
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:               bis.w   0(r14), r15
 
 @foo = external global i16
@@ -17,7 +17,7 @@ define i16 @am2(i16 %x) nounwind {
        %2 = or i16 %1,%x
        ret i16 %2
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:               bis.w   &foo, r15
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -28,7 +28,7 @@ define i8 @am3(i8 %x, i16 %n) nounwind {
        %3 = or i8 %2,%x
        ret i8 %3
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:               bis.b   bar(r14), r15
 
 define i16 @am4(i16 %x) nounwind {
@@ -36,7 +36,7 @@ define i16 @am4(i16 %x) nounwind {
        %2 = or i16 %1,%x
        ret i16 %2
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:               bis.w   &32, r15
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
@@ -45,7 +45,7 @@ define i16 @am5(i16 %x, i16* %a) nounwind {
        %3 = or i16 %2,%x
        ret i16 %3
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:               bis.w   4(r14), r15
 
 %S = type { i16, i16 }
@@ -56,7 +56,7 @@ define i16 @am6(i16 %x) nounwind {
        %2 = or i16 %1,%x
        ret i16 %2
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:               bis.w   &baz+2, r15
 
 %T = type { i16, [2 x i8] }
@@ -69,6 +69,6 @@ define i8 @am7(i8 %x, i16 %n) nounwind {
        %4 = or i8 %3,%x
        ret i8 %4
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:               bis.b   duh+2(r14), r15