Add missing register forms of instructions to the ARM CMP-folding code. This

[oota-llvm.git] / test / CodeGen / MSP430 / AddrMode-mov-xr.ll

diff --git a/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
index b8155d3a5513db52395016acf1db4cb1b1ddfabc..4b327b0578f2ef0974ffd6bb1f2bb45d82e6c511 100644 (file)
--- a/test/CodeGen/MSP430/AddrMode-mov-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+; RUN: llc < %s -march=msp430 | FileCheck %s
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
 target triple = "msp430-generic-generic"
 
@@ -26,7 +26,7 @@ define void @am3(i16 %i, i8 %a) nounwind {
        ret void
 }
 ; CHECK: am3:
-; CHECK:               mov.b   r14, &bar(r15)
+; CHECK:               mov.b   r14, bar(r15)
 
 define void @am4(i16 %a) nounwind {
        volatile store i16 %a, i16* inttoptr(i16 32 to i16*)
@@ -63,5 +63,5 @@ define void @am7(i16 %n, i8 %a) nounwind {
        ret void
 }
 ; CHECK: am7:
-; CHECK:               mov.b   r14, &duh+2(r15)
+; CHECK:               mov.b   r14, duh+2(r15)