[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / MSP430 / Inst16rm.ll

diff --git a/test/CodeGen/MSP430/Inst16rm.ll b/test/CodeGen/MSP430/Inst16rm.ll
index 57c60b68376d18a43ac0068d3bffb2207636e779..4f6998ee68dfe9d73b8cf09efd8c38d0de25a8be 100644 (file)
--- a/test/CodeGen/MSP430/Inst16rm.ll
+++ b/test/CodeGen/MSP430/Inst16rm.ll
@@ -1,37 +1,45 @@
-; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define i16 @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w &foo, r15
-       %1 = load i16* @foo
+       %1 = load i16, i16* @foo
        %2 = add i16 %a, %1
        ret i16 %2
 }
 
 define i16 @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w &foo, r15
-       %1 = load i16* @foo
+       %1 = load i16, i16* @foo
        %2 = and i16 %a, %1
        ret i16 %2
 }
 
-
 define i16 @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w &foo, r15
-       %1 = load i16* @foo
+       %1 = load i16, i16* @foo
        %2 = or i16 %a, %1
        ret i16 %2
 }
 
+define i16  @bic(i16 %a) nounwind {
+; CHECK-LABEL: bic:
+; CHECK: bic.w &foo, r15
+        %1 = load i16, i16* @foo
+        %2 = xor i16 %1, -1
+        %3 = and i16 %a, %2
+        ret i16 %3
+}
+
 define i16 @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w &foo, r15
-       %1 = load i16* @foo
+       %1 = load i16, i16* @foo
        %2 = xor i16 %a, %1
        ret i16 %2
 }