Add missing register forms of instructions to the ARM CMP-folding code. This

[oota-llvm.git] / test / CodeGen / MSP430 / Inst16rr.ll

diff --git a/test/CodeGen/MSP430/Inst16rr.ll b/test/CodeGen/MSP430/Inst16rr.ll
index 6619c518236480c1193966f95817343501565f45..2f1ba5b4f13160c53785f13d7d9a60812a56a5e4 100644 (file)
--- a/test/CodeGen/MSP430/Inst16rr.ll
+++ b/test/CodeGen/MSP430/Inst16rr.ll
@@ -29,6 +29,14 @@ define i16 @bis(i16 %a, i16 %b) nounwind {
        ret i16 %1
 }
 
+define i16 @bic(i16 %a, i16 %b) nounwind {
+; CHECK: bic:
+; CHECK: bic.w r14, r15
+        %1 = xor i16 %b, -1
+        %2 = and i16 %a, %1
+        ret i16 %2
+}
+
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK: xor:
 ; CHECK: xor.w r14, r15