Add missing register forms of instructions to the ARM CMP-folding code. This

[oota-llvm.git] / test / CodeGen / MSP430 / Inst8mr.ll

diff --git a/test/CodeGen/MSP430/Inst8mr.ll b/test/CodeGen/MSP430/Inst8mr.ll
index 950960740320ad8d99a0d3741413be06dfda6c68..428d1fa38d1a2b1934da946776c2a2a2aea82197 100644 (file)
--- a/test/CodeGen/MSP430/Inst8mr.ll
+++ b/test/CodeGen/MSP430/Inst8mr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+; RUN: llc -march=msp430 < %s | FileCheck %s
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
@@ -37,6 +37,16 @@ define void @bis(i8 %a) nounwind {
        ret void
 }
 
+define void @bic(i8 zeroext %m) nounwind {
+; CHECK: bic:
+; CHECK: bic.b   r15, &foo
+        %1 = xor i8 %m, -1
+        %2 = load i8* @foo
+        %3 = and i8 %2, %1
+        store i8 %3, i8* @foo
+        ret void
+}
+
 define void @xor(i8 %a) nounwind {
 ; CHECK: xor:
 ; CHECK: xor.b r15, &foo