[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / MSP430 / setcc.ll

diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
index 9db51cce73cb01fbd3faa8982c31eb7781b7be2d..d5a8057ddd6c49e981851fcf65994a4dcf33d5a8 100644 (file)
--- a/test/CodeGen/MSP430/setcc.ll
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -8,11 +8,11 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind {
        %t3 = zext i1 %t2 to i16
        ret i16 %t3
 }
-; CHECK: sccweqand:
+; CHECK-LABEL: sccweqand:
 ; CHECK:       bit.w   r14, r15
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  and.w   #1, r15
-; CHECK-NEXT:  xor.w   #1, r15
+; CHECK:       mov.w   r2, r15
+; CHECK:       rra.w   r15
+; CHECK:       and.w   #1, r15
 
 define i16 @sccwneand(i16 %a, i16 %b) nounwind {
        %t1 = and i16 %a, %b
@@ -20,75 +20,73 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind {
        %t3 = zext i1 %t2 to i16
        ret i16 %t3
 }
-; CHECK: sccwneand:
+; CHECK-LABEL: sccwneand:
 ; CHECK:       bit.w   r14, r15
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  and.w   #1, r15
+; CHECK:       mov.w   r2, r15
+; CHECK:       and.w   #1, r15
 
 define i16 @sccwne(i16 %a, i16 %b) nounwind {
        %t1 = icmp ne i16 %a, %b
        %t2 = zext i1 %t1 to i16
        ret i16 %t2
 }
-; CHECK:sccwne:
+; CHECK-LABEL:sccwne:
 ; CHECK:       cmp.w   r14, r15
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  rra.w   r15
-; CHECK-NEXT:  and.w   #1, r15
+; CHECK:       mov.w   r2, r12
+; CHECK:       rra.w   r12
+; CHECK:       mov.w   #1, r15
+; CHECK:       bic.w   r12, r15
 
 define i16 @sccweq(i16 %a, i16 %b) nounwind {
        %t1 = icmp eq i16 %a, %b
        %t2 = zext i1 %t1 to i16
        ret i16 %t2
 }
-; CHECK:sccweq:
+; CHECK-LABEL:sccweq:
 ; CHECK:       cmp.w   r14, r15
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  rra.w   r15
-; CHECK-NEXT:  and.w   #1, r15
-; CHECK-NEXT:  xor.w   #1, r15
+; CHECK:       mov.w   r2, r15
+; CHECK:       rra.w   r15
+; CHECK:       and.w   #1, r15
 
 define i16 @sccwugt(i16 %a, i16 %b) nounwind {
        %t1 = icmp ugt i16 %a, %b
        %t2 = zext i1 %t1 to i16
        ret i16 %t2
 }
-; CHECK:sccwugt:
+; CHECK-LABEL:sccwugt:
 ; CHECK:       cmp.w   r15, r14
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  and.w   #1, r15
-; CHECK-NEXT:  xor.w   #1, r15
+; CHECK:       mov.w   #1, r15
+; CHECK:       bic.w   r2, r15
 
 define i16 @sccwuge(i16 %a, i16 %b) nounwind {
        %t1 = icmp uge i16 %a, %b
        %t2 = zext i1 %t1 to i16
        ret i16 %t2
 }
-; CHECK:sccwuge:
+; CHECK-LABEL:sccwuge:
 ; CHECK:       cmp.w   r14, r15
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  and.w   #1, r15
+; CHECK:       mov.w   r2, r15
+; CHECK:       and.w   #1, r15
 
 define i16 @sccwult(i16 %a, i16 %b) nounwind {
        %t1 = icmp ult i16 %a, %b
        %t2 = zext i1 %t1 to i16
        ret i16 %t2
 }
-; CHECK:sccwult:
+; CHECK-LABEL:sccwult:
 ; CHECK:       cmp.w   r14, r15
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  and.w   #1, r15
-; CHECK-NEXT:  xor.w   #1, r15
+; CHECK:       mov.w   #1, r15
+; CHECK:       bic.w   r2, r15
 
 define i16 @sccwule(i16 %a, i16 %b) nounwind {
        %t1 = icmp ule i16 %a, %b
        %t2 = zext i1 %t1 to i16
        ret i16 %t2
 }
-; CHECK:sccwule:
+; CHECK-LABEL:sccwule:
 ; CHECK:       cmp.w   r15, r14
-; CHECK-NEXT:  mov.w   r2, r15
-; CHECK-NEXT:  and.w   #1, r15
+; CHECK:       mov.w   r2, r15
+; CHECK:       and.w   #1, r15
 
 define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
        %t1 = icmp sgt i16 %a, %b