Lower AVX v4i64->v4i32 truncate to one shuffle.

[oota-llvm.git] / test / CodeGen / Mips / const-mult.ll

diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll
index d818044decb5194c3a9a85ad841633f5a1b78de4..186202141dcbd0eb1d68900f8013d035e44890c7 100644 (file)
--- a/test/CodeGen/Mips/const-mult.ll
+++ b/test/CodeGen/Mips/const-mult.ll
@@ -1,8 +1,7 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
+; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64
 
-; CHECK: mul5_32:
+; CHECK-LABEL: mul5_32:
 ; CHECK: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
 
@@ -12,7 +11,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK:     mul27_32:
+; CHECK-LABEL:     mul27_32:
 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
@@ -24,7 +23,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK:     muln2147483643_32:
+; CHECK-LABEL:     muln2147483643_32:
 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
@@ -36,11 +35,11 @@ entry:
   ret i32 %mul
 }
 
-; CHECK64:     muln9223372036854775805_64:
-; CHECK64-DAG: sll $[[R0:[0-9]+]], $4, 1
-; CHECK64-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
-; CHECK64-DAG: sll $[[R2:[0-9]+]], $4, 63
-; CHECK64:     addu ${{[0-9]+}}, $[[R2]], $[[R1]]
+; CHECK64-LABEL:     muln9223372036854775805_64:
+; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
+; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
+; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
+; CHECK64:     daddu ${{[0-9]+}}, $[[R2]], $[[R1]]
 
 define i64 @muln9223372036854775805_64(i64 %a) {
 entry: