-; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
define i64 @f14(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: ddiv $zero
+; CHECK-LABEL: f14:
+; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
+; CHECK: teq $[[R0]], $zero, 7
; CHECK: mflo
%div = sdiv i64 %a, %b
ret i64 %div
define i64 @f15(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: ddivu $zero
+; CHECK-LABEL: f15:
+; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
+; CHECK: teq $[[R0]], $zero, 7
; CHECK: mflo
%div = udiv i64 %a, %b
ret i64 %div
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: ddiv $zero
+; CHECK-LABEL: f16:
+; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
+; CHECK: teq $[[R0]], $zero, 7
; CHECK: mfhi
%rem = srem i64 %a, %b
ret i64 %rem
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: ddivu $zero
+; CHECK-LABEL: f17:
+; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
+; CHECK: teq $[[R0]], $zero, 7
; CHECK: mfhi
%rem = urem i64 %a, %b
ret i64 %rem
}
-declare i64 @llvm.ctlz.i64(i64) nounwind readnone
+declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
-; CHECK: dclz $2, $4
define i64 @f18(i64 %X) nounwind readnone {
entry:
- %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X)
+; CHECK: dclz $2, $4
+ %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
-; CHECK: dclo $2, $4
define i64 @f19(i64 %X) nounwind readnone {
entry:
+; CHECK: dclo $2, $4
%neg = xor i64 %X, -1
- %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg)
+ %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
}