MIR Serialization: Serialize the sub register indices.

[oota-llvm.git] / test / CodeGen / Mips / msa / elm_shift_slide.ll

diff --git a/test/CodeGen/Mips/msa/elm_shift_slide.ll b/test/CodeGen/Mips/msa/elm_shift_slide.ll
index 00a6544b120700439cfdbf4f682bc808b00c706d..87f15f1a8c9274b7079172a04c5a54b6bb8f751d 100644 (file)
--- a/test/CodeGen/Mips/msa/elm_shift_slide.ll
+++ b/test/CodeGen/Mips/msa/elm_shift_slide.ll
@@ -10,8 +10,8 @@
 
 define void @llvm_mips_sldi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_sldi_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sldi_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sldi_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sldi_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sldi_b_RES
   ret void
@@ -31,8 +31,8 @@ declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_sldi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_sldi_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sldi_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sldi_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sldi_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sldi_h_RES
   ret void
@@ -52,8 +52,8 @@ declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_sldi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_sldi_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sldi_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sldi_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sldi_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sldi_w_RES
   ret void
@@ -73,8 +73,8 @@ declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_sldi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_sldi_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sldi_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sldi_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sldi_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sldi_d_RES
   ret void
@@ -93,7 +93,7 @@ declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_splati_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_splati_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_splati_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.splati.b(<16 x i8> %0, i32 1)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_splati_b_RES
   ret void
@@ -112,7 +112,7 @@ declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_splati_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_splati_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_splati_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.splati.h(<8 x i16> %0, i32 1)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_splati_h_RES
   ret void
@@ -131,7 +131,7 @@ declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_splati_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_splati_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_splati_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.splati.w(<4 x i32> %0, i32 1)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_splati_w_RES
   ret void
@@ -150,7 +150,7 @@ declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_splati_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_splati_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_splati_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.splati.d(<2 x i64> %0, i32 1)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_splati_d_RES
   ret void