-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
-
+; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
; All test functions do the same thing - they return the first variable
; argument.
-; All CHECK's do the same thing - they check whether variable arguments from
-; registers are placed on correct stack locations, and whether the first
+; All CHECK's do the same thing - they check whether variable arguments from
+; registers are placed on correct stack locations, and whether the first
; variable argument is returned from the correct stack location.
ret i32 %tmp
; CHECK: va1:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: sw $5, 36($sp)
-; CHECK: sw $6, 40($sp)
-; CHECK: sw $7, 44($sp)
-; CHECK: lw $2, 36($sp)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
+; CHECK: lw $2, 20($sp)
}
-; check whether the variable double argument will be accessed from the 8-byte
-; aligned location (i.e. whether the address is computed by adding 7 and
+; check whether the variable double argument will be accessed from the 8-byte
+; aligned location (i.e. whether the address is computed by adding 7 and
; clearing lower 3 bits)
define double @va2(i32 %a, ...) nounwind {
entry:
ret double %tmp
; CHECK: va2:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: addiu $2, $sp, 44
-; CHECK: sw $5, 44($sp)
-; CHECK: sw $6, 48($sp)
-; CHECK: sw $7, 52($sp)
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $3, $3, $5
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
ret i32 %tmp
; CHECK: va3:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: sw $6, 48($sp)
-; CHECK: sw $7, 52($sp)
-; CHECK: lw $2, 48($sp)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: lw $2, 24($sp)
}
; double
ret double %tmp
; CHECK: va4:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $6, 56($sp)
-; CHECK: sw $7, 60($sp)
-; CHECK: addiu $3, $sp, 56
-; CHECK: addiu $6, $3, 7
-; CHECK: addiu $7, $zero, -8
-; CHECK: and $2, $6, $7
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: sw $6, 32($sp)
+; CHECK: addiu ${{[0-9]+}}, $sp, 32
+; CHECK: ldc1 $f0, 32($sp)
}
; int
ret i32 %tmp
; CHECK: va5:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: sw $7, 52($sp)
-; CHECK: lw $2, 52($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: lw $2, 36($sp)
}
; double
ret double %tmp
; CHECK: va6:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $7, 60($sp)
-; CHECK: addiu $2, $sp, 60
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $3, $3, $4
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
ret i32 %tmp
; CHECK: va7:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: lw $2, 56($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: lw $2, 40($sp)
}
; double
ret double %tmp
; CHECK: va8:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: addiu $3, $sp, 64
-; CHECK: addiu $4, $3, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $2, $4, $5
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: addiu ${{[0-9]+}}, $sp, 48
+; CHECK: ldc1 $f0, 48($sp)
}
; int
ret i32 %tmp
; CHECK: va9:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: lw $2, 76($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: lw $2, 52($sp)
}
; double
ret double %tmp
; CHECK: va10:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $3, $sp, 76
-; CHECK: addiu $2, $3, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $2, $2, $4
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}