[x32] Fix FrameIndex check in SelectLEA64_32Addr

[oota-llvm.git] / test / CodeGen / Mips / selectcc.ll

diff --git a/test/CodeGen/Mips/selectcc.ll b/test/CodeGen/Mips/selectcc.ll
index a17517e7d1455b3be7f292662b5a31c566689060..9790a0a3e4110cb0d632f197544981bb09bd4b25 100644 (file)
--- a/test/CodeGen/Mips/selectcc.ll
+++ b/test/CodeGen/Mips/selectcc.ll
@@ -1,4 +1,7 @@
-; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mcpu=mips32 < %s
+; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
+; RUN: llc -march=mipsel -mcpu=mips32r2 < %s
+; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
 
 @gf0 = external global float
 @gf1 = external global float
@@ -7,6 +10,19 @@
 
 define float @select_cc_f32(float %a, float %b) nounwind {
 entry:
+; SOURCE-SCHED: lui
+; SOURCE-SCHED: addiu
+; SOURCE-SCHED: addu
+; SOURCE-SCHED: lw
+; SOURCE-SCHED: sw
+; SOURCE-SCHED: lw
+; SOURCE-SCHED: lui
+; SOURCE-SCHED: sw
+; SOURCE-SCHED: lw
+; SOURCE-SCHED: lwc1
+; SOURCE-SCHED: mtc1
+; SOURCE-SCHED: c.olt.s
+; SOURCE-SCHED: jr
   store float 0.000000e+00, float* @gf0, align 4
   store float 1.000000e+00, float* @gf1, align 4
   %cmp = fcmp olt float %a, %b