[PowerPC] v4i32 is a VSRCRegClass

[oota-llvm.git] / test / CodeGen / Mips / seleqk.ll

diff --git a/test/CodeGen/Mips/seleqk.ll b/test/CodeGen/Mips/seleqk.ll
index 3ca622d5d8fe24e914eebb4f06572d006248f1cc..2eeaa9e33738fd89b85b045a3d438de232b70f57 100644 (file)
--- a/test/CodeGen/Mips/seleqk.ll
+++ b/test/CodeGen/Mips/seleqk.ll
@@ -12,61 +12,61 @@
 
 define void @calc_seleqk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
 entry:
-  %0 = load i32* @a, align 4
+  %0 = load i32, i32* @a, align 4
   %cmp = icmp eq i32 %0, 1
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %entry
-  %1 = load i32* @t, align 4
+  %1 = load i32, i32* @t, align 4
   br label %cond.end
 
 cond.false:                                       ; preds = %entry
-  %2 = load i32* @f, align 4
+  %2 = load i32, i32* @f, align 4
   br label %cond.end
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
   store i32 %cond, i32* @z1, align 4
-  %3 = load i32* @a, align 4
+  %3 = load i32, i32* @a, align 4
   %cmp1 = icmp eq i32 %3, 1000
   br i1 %cmp1, label %cond.true2, label %cond.false3
 
 cond.true2:                                       ; preds = %cond.end
-  %4 = load i32* @f, align 4
+  %4 = load i32, i32* @f, align 4
   br label %cond.end4
 
 cond.false3:                                      ; preds = %cond.end
-  %5 = load i32* @t, align 4
+  %5 = load i32, i32* @t, align 4
   br label %cond.end4
 
 cond.end4:                                        ; preds = %cond.false3, %cond.true2
   %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
   store i32 %cond5, i32* @z2, align 4
-  %6 = load i32* @b, align 4
+  %6 = load i32, i32* @b, align 4
   %cmp6 = icmp eq i32 %6, 3
   br i1 %cmp6, label %cond.true7, label %cond.false8
 
 cond.true7:                                       ; preds = %cond.end4
-  %7 = load i32* @f, align 4
+  %7 = load i32, i32* @f, align 4
   br label %cond.end9
 
 cond.false8:                                      ; preds = %cond.end4
-  %8 = load i32* @t, align 4
+  %8 = load i32, i32* @t, align 4
   br label %cond.end9
 
 cond.end9:                                        ; preds = %cond.false8, %cond.true7
   %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
   store i32 %cond10, i32* @z3, align 4
-  %9 = load i32* @b, align 4
+  %9 = load i32, i32* @b, align 4
   %cmp11 = icmp eq i32 %9, 1000
   br i1 %cmp11, label %cond.true12, label %cond.false13
 
 cond.true12:                                      ; preds = %cond.end9
-  %10 = load i32* @t, align 4
+  %10 = load i32, i32* @t, align 4
   br label %cond.end14
 
 cond.false13:                                     ; preds = %cond.end9
-  %11 = load i32* @f, align 4
+  %11 = load i32, i32* @f, align 4
   br label %cond.end14
 
 cond.end14:                                       ; preds = %cond.false13, %cond.true12