[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / 2006-01-20-ShiftPartsCrash.ll

diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
index fbf254082ee0e82e0d005bb0b73293877b206a94..d20e3b05c09162934d479ff9ce35fbb7d03f0052 100644 (file)
--- a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
+++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
@@ -1,14 +1,15 @@
 ; RUN: llc < %s
+; REQUIRES: default_triple
 
 define void @iterative_hash_host_wide_int() {
         %zero = alloca i32              ; <i32*> [#uses=2]
         %b = alloca i32         ; <i32*> [#uses=1]
         store i32 0, i32* %zero
-        %tmp = load i32* %zero          ; <i32> [#uses=1]
+        %tmp = load i32, i32* %zero          ; <i32> [#uses=1]
         %tmp5 = bitcast i32 %tmp to i32         ; <i32> [#uses=1]
         %tmp6.u = add i32 %tmp5, 32             ; <i32> [#uses=1]
         %tmp6 = bitcast i32 %tmp6.u to i32              ; <i32> [#uses=1]
-        %tmp7 = load i64* null          ; <i64> [#uses=1]
+        %tmp7 = load i64, i64* null          ; <i64> [#uses=1]
         %tmp6.upgrd.1 = trunc i32 %tmp6 to i8           ; <i8> [#uses=1]
         %shift.upgrd.2 = zext i8 %tmp6.upgrd.1 to i64           ; <i64> [#uses=1]
         %tmp8 = ashr i64 %tmp7, %shift.upgrd.2          ; <i64> [#uses=1]