[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

[oota-llvm.git] / test / CodeGen / PowerPC / 2006-09-28-shift_64.ll

diff --git a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
index d5da348bcf7755fec85bfb68427dd5be97dab653..f748a8bf1d6c566f4be744652a3d6c808658ca6c 100644 (file)
--- a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
+++ b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
@@ -1,27 +1,25 @@
-; RUN: llvm-as < %s | llc -march=ppc64
-target endian = big
-target pointersize = 64
-target triple = "powerpc64-apple-darwin8"
+; RUN: llc < %s -march=ppc64
 
-implementation   ; Functions:
+target datalayout = "E-p:64:64"
+target triple = "powerpc64-apple-darwin8"
 
-void %glArrayElement_CompExec() {
+define void @glArrayElement_CompExec() {
 entry:
-       %tmp3 = and ulong 0, 18446744073701163007               ; <ulong> [#uses=1]
-       br label %cond_true24
-
-cond_false:            ; preds = %cond_true24
-       ret void
-
-cond_true24:           ; preds = %cond_true24, %entry
-       %indvar.ph = phi uint [ 0, %entry ], [ %indvar.next, %cond_true24 ]             ; <uint> [#uses=1]
-       %indvar = add uint 0, %indvar.ph                ; <uint> [#uses=2]
-       %code.0 = cast uint %indvar to ubyte            ; <ubyte> [#uses=1]
-       %tmp5 = add ubyte %code.0, 16           ; <ubyte> [#uses=1]
-       %tmp7 = shr ulong %tmp3, ubyte %tmp5            ; <ulong> [#uses=1]
-       %tmp7 = cast ulong %tmp7 to int         ; <int> [#uses=1]
-       %tmp8 = and int %tmp7, 1                ; <int> [#uses=1]
-       %tmp8 = seteq int %tmp8, 0              ; <bool> [#uses=1]
-       %indvar.next = add uint %indvar, 1              ; <uint> [#uses=1]
-       br bool %tmp8, label %cond_false, label %cond_true24
+        %tmp3 = and i64 0, -8388609             ; <i64> [#uses=1]
+        br label %cond_true24
+cond_false:             ; preds = %cond_true24
+        ret void
+cond_true24:            ; preds = %cond_true24, %entry
+        %indvar.ph = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true24 ]              ; <i32> [#uses=1]
+        %indvar = add i32 0, %indvar.ph         ; <i32> [#uses=2]
+        %code.0 = trunc i32 %indvar to i8               ; <i8> [#uses=1]
+        %tmp5 = add i8 %code.0, 16              ; <i8> [#uses=1]
+        %shift.upgrd.1 = zext i8 %tmp5 to i64           ; <i64> [#uses=1]
+        %tmp7 = lshr i64 %tmp3, %shift.upgrd.1          ; <i64> [#uses=1]
+        %tmp7.upgrd.2 = trunc i64 %tmp7 to i32          ; <i32> [#uses=1]
+        %tmp8 = and i32 %tmp7.upgrd.2, 1                ; <i32> [#uses=1]
+        %tmp8.upgrd.3 = icmp eq i32 %tmp8, 0            ; <i1> [#uses=1]
+        %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=1]
+        br i1 %tmp8.upgrd.3, label %cond_false, label %cond_true24
 }
+