[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / 2006-12-07-LargeAlloca.ll

diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
index be3b86308f13a663fd62a335b2b5d35b85120762..c064c273173f7862db36c5494db65cf12a3a8b0e 100644 (file)
--- a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
+++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
@@ -1,6 +1,7 @@
-; RUN: llvm-as < %s | llc -march=ppc64
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc 
+; RUN: llc < %s -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s 
+; REQUIRES: default_triple
 
 define void @bitap() {
 entry:
@@ -14,7 +15,7 @@ bb19:           ; preds = %entry
 bb12.i:         ; preds = %bb12.i, %bb19
         %i.0.i = phi i32 [ %tmp11.i, %bb12.i ], [ 0, %bb19 ]            ; <i32> [#uses=2]
         %gep.upgrd.1 = zext i32 %i.0.i to i64           ; <i64> [#uses=1]
-        %tmp9.i = getelementptr [256 x i32]* %RMask.i, i32 0, i64 %gep.upgrd.1          ; <i32*> [#uses=1]
+        %tmp9.i = getelementptr [256 x i32], [256 x i32]* %RMask.i, i32 0, i64 %gep.upgrd.1          ; <i32*> [#uses=1]
         store i32 0, i32* %tmp9.i
         %tmp11.i = add i32 %i.0.i, 1            ; <i32> [#uses=1]
         br label %bb12.i