[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / 2007-01-31-InlineAsmAddrMode.ll

diff --git a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
index c4d57639872a91475650a51419e65ce6a1f8d3ad..6ce32da2f740eeb2dfc6f9a7fe5f442020711c2c 100644 (file)
--- a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
+++ b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 &&
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
 
 ; Test two things: 1) that a frameidx can be rewritten in an inline asm
 ; 2) that inline asms can handle reg+imm addr modes.
@@ -10,7 +10,7 @@
 define void @test1() {
 entry:
        %Out = alloca %struct.A, align 4                ; <%struct.A*> [#uses=1]
-       %tmp2 = getelementptr %struct.A* %Out, i32 0, i32 1
+       %tmp2 = getelementptr %struct.A, %struct.A* %Out, i32 0, i32 1
        %tmp5 = call i32 asm "lwbrx $0, $1", "=r,m"(i32* %tmp2 )
        ret void
 }
@@ -18,7 +18,7 @@ entry:
 define void @test2() {
 entry:
        %Out = alloca %struct.A, align 4                ; <%struct.A*> [#uses=1]
-       %tmp2 = getelementptr %struct.A* %Out, i32 0, i32 0             ; <i32*> [#uses=1]
+       %tmp2 = getelementptr %struct.A, %struct.A* %Out, i32 0, i32 0          ; <i32*> [#uses=1]
        %tmp5 = call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,m"( i8* null, i32 0, i32* %tmp2 )             ; <i32> [#uses=0]
        ret void
 }