[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / 2007-11-19-VectorSplitting.ll

diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
index aca0faaa4e41b3225f438f285d77877244cc68c2..aa39dfd0374870ec154bb29bf90e6bbbf760617a 100644 (file)
--- a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
+++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
@@ -1,12 +1,13 @@
-; RUN: llvm-as < %s | llc 
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s 
+; RUN: llc < %s -march=ppc32 -mcpu=g3
+; RUN: llc < %s -march=ppc32 -mcpu=g5
 ; PR1811
+; REQUIRES: default_triple
 
 define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>*
 %CONST) {
 entry:
-        %input2 = load <4 x float>* null, align 16               ; <<4 x float>>
+        %input2 = load <4 x float>, <4 x float>* null, align 16               ; <<4 x float>>
                %shuffle7 = shufflevector <4 x float> %input2, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >         ; <<4 x float>> [#uses=1]
 
         %mul1 = fmul <4 x float> %shuffle7, zeroinitializer              ; <<4 x