[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / 2008-03-05-RegScavengerAssert.ll

diff --git a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
index 8101a35a4fb4fce5384ce31812c446e790386f93..863b02528e1e22c8f1c076406ea8cee68cbaf254 100644 (file)
--- a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
+++ b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
 
 declare i8* @bar(i32)
 
@@ -6,7 +6,7 @@ define void @foo(i8* %pp) nounwind  {
 entry:
        %tmp2 = tail call i8* @bar( i32 14 ) nounwind           ; <i8*> [#uses=0]
        %tmp28 = bitcast i8* %pp to void ()**           ; <void ()**> [#uses=1]
-       %tmp38 = load void ()** %tmp28, align 4         ; <void ()*> [#uses=2]
+       %tmp38 = load void ()*, void ()** %tmp28, align 4               ; <void ()*> [#uses=2]
        br i1 false, label %bb34, label %bb25
 bb25:          ; preds = %entry
        %tmp30 = bitcast void ()* %tmp38 to void (i8*)*         ; <void (i8*)*> [#uses=1]