[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / 2008-07-15-SignExtendInreg.ll

diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
index 32e36427c5e6f5b5bdafd6f85e93d98b89818030..53639e7ceb04a00ff56b521416c70fe2736a3f3c 100644 (file)
--- a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
+++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc-apple-darwin9"
 
-define i16 @t(i16* %dct) signext nounwind  {
+define signext i16 @t(i16* %dct)  nounwind  {
 entry:
-         load i16* null, align 2         ; <i16>:0 [#uses=2]
+         load i16, i16* null, align 2         ; <i16>:0 [#uses=2]
          lshr i16 %0, 11         ; <i16>:1 [#uses=0]
          trunc i16 %0 to i8              ; <i8>:2 [#uses=1]
          sext i8 %2 to i16               ; <i16>:3 [#uses=1]