[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / asm-constraints.ll

diff --git a/test/CodeGen/PowerPC/asm-constraints.ll b/test/CodeGen/PowerPC/asm-constraints.ll
index 9bf8b75e0ace704a34aea881084e3aacd2dac318..2d9b0eb591d3cea0b57dfa18525da88d19f02d32 100644 (file)
--- a/test/CodeGen/PowerPC/asm-constraints.ll
+++ b/test/CodeGen/PowerPC/asm-constraints.ll
@@ -23,7 +23,7 @@ entry:
   %addr.addr = alloca i8*, align 8
   store i32 %result, i32* %result.addr, align 4
   store i8* %addr, i8** %addr.addr, align 8
-  %0 = load i8** %addr.addr, align 8
+  %0 = load i8*, i8** %addr.addr, align 8
   %1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !1
   store i32 %1, i32* %result.addr, align 4
   ret void
@@ -31,7 +31,7 @@ entry:
 
 ; CHECK-LABEL: @foo
 ; CHECK: ld [[REG:[0-9]+]], 0(4)
-; CHECK: cmpw 0, [[REG]], [[REG]]
+; CHECK: cmpw [[REG]], [[REG]]
 ; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
 ; CHECK: .Ltmp[[TMP]]:
 ; CHECK: isync