[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / ctrloop-i64.ll

diff --git a/test/CodeGen/PowerPC/ctrloop-i64.ll b/test/CodeGen/PowerPC/ctrloop-i64.ll
index 6aa3dba68a54740b0bedbba537a3da6c277ba7ef..5c66a6865ae2c47acdcec3aae78a974b60516992 100644 (file)
--- a/test/CodeGen/PowerPC/ctrloop-i64.ll
+++ b/test/CodeGen/PowerPC/ctrloop-i64.ll
@@ -11,7 +11,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
   %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = udiv i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
@@ -33,7 +33,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
   %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = sdiv i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
@@ -55,7 +55,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
   %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = urem i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1
@@ -77,7 +77,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ]
   %arrayidx = getelementptr inbounds i64, i64* %n, i32 %i.06
-  %0 = load i64* %arrayidx, align 8
+  %0 = load i64, i64* %arrayidx, align 8
   %conv = srem i64 %x.05, %d
   %conv1 = add i64 %conv, %0
   %inc = add nsw i32 %i.06, 1