[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / fast-isel-ext.ll

diff --git a/test/CodeGen/PowerPC/fast-isel-ext.ll b/test/CodeGen/PowerPC/fast-isel-ext.ll
index 6fd3b4035122d5d20a996c68197150dcaa5047d4..ce8ac440b79cbcba045ab39bb4a4cf2ca4f1d49c 100644 (file)
--- a/test/CodeGen/PowerPC/fast-isel-ext.ll
+++ b/test/CodeGen/PowerPC/fast-isel-ext.ll
@@ -2,35 +2,35 @@
 
 ; zext
 
-define i32 @zext_8_32(i8 %a) nounwind ssp {
+define i32 @zext_8_32(i8 %a) nounwind {
 ; ELF64: zext_8_32
   %r = zext i8 %a to i32
 ; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
   ret i32 %r
 }
 
-define i32 @zext_16_32(i16 %a) nounwind ssp {
+define i32 @zext_16_32(i16 %a) nounwind {
 ; ELF64: zext_16_32
   %r = zext i16 %a to i32
 ; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
   ret i32 %r
 }
 
-define i64 @zext_8_64(i8 %a) nounwind ssp {
+define i64 @zext_8_64(i8 %a) nounwind {
 ; ELF64: zext_8_64
   %r = zext i8 %a to i64
 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
   ret i64 %r
 }
 
-define i64 @zext_16_64(i16 %a) nounwind ssp {
+define i64 @zext_16_64(i16 %a) nounwind {
 ; ELF64: zext_16_64
   %r = zext i16 %a to i64
 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
   ret i64 %r
 }
 
-define i64 @zext_32_64(i32 %a) nounwind ssp {
+define i64 @zext_32_64(i32 %a) nounwind {
 ; ELF64: zext_32_64
   %r = zext i32 %a to i64
 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
@@ -39,35 +39,35 @@ define i64 @zext_32_64(i32 %a) nounwind ssp {
 
 ; sext
 
-define i32 @sext_8_32(i8 %a) nounwind ssp {
+define i32 @sext_8_32(i8 %a) nounwind {
 ; ELF64: sext_8_32
   %r = sext i8 %a to i32
 ; ELF64: extsb
   ret i32 %r
 }
 
-define i32 @sext_16_32(i16 %a) nounwind ssp {
+define i32 @sext_16_32(i16 %a) nounwind {
 ; ELF64: sext_16_32
   %r = sext i16 %a to i32
 ; ELF64: extsh
   ret i32 %r
 }
 
-define i64 @sext_8_64(i8 %a) nounwind ssp {
+define i64 @sext_8_64(i8 %a) nounwind {
 ; ELF64: sext_8_64
   %r = sext i8 %a to i64
 ; ELF64: extsb
   ret i64 %r
 }
 
-define i64 @sext_16_64(i16 %a) nounwind ssp {
+define i64 @sext_16_64(i16 %a) nounwind {
 ; ELF64: sext_16_64
   %r = sext i16 %a to i64
 ; ELF64: extsh
   ret i64 %r
 }
 
-define i64 @sext_32_64(i32 %a) nounwind ssp {
+define i64 @sext_32_64(i32 %a) nounwind {
 ; ELF64: sext_32_64
   %r = sext i32 %a to i64
 ; ELF64: extsw