[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / fast-isel-redefinition.ll

diff --git a/test/CodeGen/PowerPC/fast-isel-redefinition.ll b/test/CodeGen/PowerPC/fast-isel-redefinition.ll
index 72422bda4433da799ffdc73beb5f864f9abd3b1a..19392c938e150d26e341eee9d26bb8fa94be48b7 100644 (file)
--- a/test/CodeGen/PowerPC/fast-isel-redefinition.ll
+++ b/test/CodeGen/PowerPC/fast-isel-redefinition.ll
@@ -1,10 +1,10 @@
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
 ; This isn't exactly a useful set of command-line options, but check that it
 ; doesn't crash.  (It crashed formerly on ARM, and proved useful in
 ; discovering a bug on PowerPC as well.)
 
-define i32 @f(i32* %x) nounwind ssp {
-  %y = getelementptr inbounds i32* %x, i32 5000
-  %tmp103 = load i32* %y, align 4
+define i32 @f(i32* %x) nounwind {
+  %y = getelementptr inbounds i32, i32* %x, i32 5000
+  %tmp103 = load i32, i32* %y, align 4
   ret i32 %tmp103
 }