[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / mcm-5.ll

diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll
index 10d89f521564fc04b90258d865272c2d53525c43..19adbe5b7d938fda327e46322e26e08ce84dfd88 100644 (file)
--- a/test/CodeGen/PowerPC/mcm-5.ll
+++ b/test/CodeGen/PowerPC/mcm-5.ll
@@ -1,6 +1,7 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -code-model=large <%s | FileCheck %s
 
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
 ; for loading the address of a jump table from the TOC.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
@@ -10,7 +11,7 @@ define signext i32 @test_jump_table(i32 signext %i) nounwind {
 entry:
   %i.addr = alloca i32, align 4
   store i32 %i, i32* %i.addr, align 4
-  %0 = load i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
   switch i32 %0, label %sw.default [
     i32 3, label %sw.bb
     i32 4, label %sw.bb1
@@ -22,35 +23,35 @@ sw.default:                                       ; preds = %entry
   br label %sw.epilog
 
 sw.bb:                                            ; preds = %entry
-  %1 = load i32* %i.addr, align 4
+  %1 = load i32, i32* %i.addr, align 4
   %mul = mul nsw i32 %1, 7
   store i32 %mul, i32* %i.addr, align 4
   br label %sw.bb1
 
 sw.bb1:                                           ; preds = %entry, %sw.bb
-  %2 = load i32* %i.addr, align 4
+  %2 = load i32, i32* %i.addr, align 4
   %dec = add nsw i32 %2, -1
   store i32 %dec, i32* %i.addr, align 4
   br label %sw.bb2
 
 sw.bb2:                                           ; preds = %entry, %sw.bb1
-  %3 = load i32* %i.addr, align 4
+  %3 = load i32, i32* %i.addr, align 4
   %add = add nsw i32 %3, 3
   store i32 %add, i32* %i.addr, align 4
   br label %sw.bb3
 
 sw.bb3:                                           ; preds = %entry, %sw.bb2
-  %4 = load i32* %i.addr, align 4
+  %4 = load i32, i32* %i.addr, align 4
   %shl = shl i32 %4, 1
   store i32 %shl, i32* %i.addr, align 4
   br label %sw.epilog
 
 sw.epilog:                                        ; preds = %sw.bb3, %sw.default
-  %5 = load i32* %i.addr, align 4
+  %5 = load i32, i32* %i.addr, align 4
   ret i32 %5
 }
 
-; CHECK: test_jump_table:
+; CHECK-LABEL: test_jump_table:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]]