AArch64: make inexact signalling on round Darwin-specific

[oota-llvm.git] / test / CodeGen / PowerPC / mcm-7.ll

diff --git a/test/CodeGen/PowerPC/mcm-7.ll b/test/CodeGen/PowerPC/mcm-7.ll
index 0dd39ee4109d25d4f2f982a51774a25442032406..9c8158df77b3e5e5b27b068e19f4a389b3fd6abe 100644 (file)
--- a/test/CodeGen/PowerPC/mcm-7.ll
+++ b/test/CodeGen/PowerPC/mcm-7.ll
@@ -11,14 +11,14 @@ define i8* @test_fnaddr() nounwind {
 entry:
   %func = alloca i32 (i32)*, align 8
   store i32 (i32)* @foo, i32 (i32)** %func, align 8
-  %0 = load i32 (i32)** %func, align 8
+  %0 = load i32 (i32)*, i32 (i32)** %func, align 8
   %1 = bitcast i32 (i32)* %0 to i8*
   ret i8* %1
 }
 
 declare signext i32 @foo(i32 signext)
 
-; CHECK: test_fnaddr:
+; CHECK-LABEL: test_fnaddr:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: .section .toc