Add Hardware Transactional Memory (HTM) Support

[oota-llvm.git] / test / CodeGen / PowerPC / ppc64-anyregcc.ll

diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll
index 7cd3c4b3820008826585e5b5a37129af96d38562..ab2feb649813ee7186bace2dee0b39823ad2a41f 100644 (file)
--- a/test/CodeGen/PowerPC/ppc64-anyregcc.ll
+++ b/test/CodeGen/PowerPC/ppc64-anyregcc.ll
@@ -2,6 +2,31 @@
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
+; CHECK-LABEL: test:
+; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: property_access1:
+; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: property_access2:
+; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: property_access3:
+; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: anyreg_test1:
+; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: anyreg_test2:
+; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: patchpoint_spilldef:
+; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
+
+; CHECK-LABEL: patchpoint_spillargs:
+; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
+
+
 ; Stackmap Header: no constants - 6 callsites
 ; CHECK-LABEL: .section        .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
@@ -26,9 +51,9 @@ target triple = "powerpc64-unknown-linux-gnu"
 ; CHECK-NEXT:   .quad property_access3
 ; CHECK-NEXT:   .quad 128
 ; CHECK-NEXT:   .quad anyreg_test1
-; CHECK-NEXT:   .quad 160
+; CHECK-NEXT:   .quad 144
 ; CHECK-NEXT:   .quad anyreg_test2
-; CHECK-NEXT:   .quad 160
+; CHECK-NEXT:   .quad 144
 ; CHECK-NEXT:   .quad patchpoint_spilldef
 ; CHECK-NEXT:   .quad 256
 ; CHECK-NEXT:   .quad patchpoint_spillargs
@@ -36,7 +61,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 
 ; test
-; CHECK-LABEL:  .long   .L{{.*}}-.L.test
+; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 3 locations
 ; CHECK-NEXT:   .short  3
@@ -62,7 +87,7 @@ entry:
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access1
+; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
@@ -84,7 +109,7 @@ entry:
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access2
+; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
@@ -107,7 +132,7 @@ entry:
 }
 
 ; property access 3 - %obj is a frame index
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access3
+; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
@@ -130,7 +155,7 @@ entry:
 }
 
 ; anyreg_test1
-; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test1
+; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
@@ -212,7 +237,7 @@ entry:
 }
 
 ; anyreg_test2
-; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test2
+; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
@@ -297,7 +322,7 @@ entry:
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
-; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spilldef
+; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 3
 ; Loc 0: Register (some register that will be spilled to the stack)
@@ -327,7 +352,7 @@ entry:
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;
-; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spillargs
+; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 5
 ; Loc 0: Return a register