[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

[oota-llvm.git] / test / CodeGen / PowerPC / rm-zext.ll

diff --git a/test/CodeGen/PowerPC/rm-zext.ll b/test/CodeGen/PowerPC/rm-zext.ll
index 291b7919280def4014f5de76e55ca5a4d9aa242c..97c546c0145fe4600119769a54e2c966344172e0 100644 (file)
--- a/test/CodeGen/PowerPC/rm-zext.ll
+++ b/test/CodeGen/PowerPC/rm-zext.ll
@@ -40,12 +40,12 @@ entry:
 }
 
 ; Function Attrs: nounwind readnone
-declare i32 @llvm.bswap.i32(i32) #1
+declare i32 @llvm.bswap.i32(i32) #0
 
 ; Function Attrs: nounwind readonly
-define zeroext i32 @bs32(i32* nocapture readonly %x) #0 {
+define zeroext i32 @bs32(i32* nocapture readonly %x) #1 {
 entry:
-  %0 = load i32* %x, align 4
+  %0 = load i32, i32* %x, align 4
   %1 = tail call i32 @llvm.bswap.i32(i32 %0)
   ret i32 %1
 
@@ -55,9 +55,9 @@ entry:
 }
 
 ; Function Attrs: nounwind readonly
-define zeroext i16 @bs16(i16* nocapture readonly %x) #0 {
+define zeroext i16 @bs16(i16* nocapture readonly %x) #1 {
 entry:
-  %0 = load i16* %x, align 2
+  %0 = load i16, i16* %x, align 2
   %1 = tail call i16 @llvm.bswap.i16(i16 %0)
   ret i16 %1
 
@@ -67,7 +67,23 @@ entry:
 }
 
 ; Function Attrs: nounwind readnone
-declare i16 @llvm.bswap.i16(i16) #1
+declare i16 @llvm.bswap.i16(i16) #0
+
+; Function Attrs: nounwind readnone
+define zeroext i32 @ctlz32(i32 zeroext %x) #0 {
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+  ret i32 %0
+
+; CHECK-LABEL: @ctlz32
+; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ctlz.i32(i32, i1) #0
+
 
 attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind readonly }