[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / rotl-2.ll

diff --git a/test/CodeGen/PowerPC/rotl-2.ll b/test/CodeGen/PowerPC/rotl-2.ll
index ce7a24c0b07b0165b4bd3700f89e9a7941217e3d..86539b6c119c33e7145255ded9f18dc480c5f4f7 100644 (file)
--- a/test/CodeGen/PowerPC/rotl-2.ll
+++ b/test/CodeGen/PowerPC/rotl-2.ll
@@ -1,6 +1,7 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 4
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep or
+; RUN: llc < %s -march=ppc32  | grep rotlwi | count 2
+; RUN: llc < %s -march=ppc32  | grep clrlwi | count 2
+; RUN: llc < %s -march=ppc32  | grep rotlw | count 4
+; RUN: llc < %s -march=ppc32  | not grep or
 
 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
        %shift.upgrd.1 = zext i8 %Amt to i32            ; <i32> [#uses=1]