[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / split-index-tc.ll

diff --git a/test/CodeGen/PowerPC/split-index-tc.ll b/test/CodeGen/PowerPC/split-index-tc.ll
index 1b27be7cf2630219e93b253c4e19c081b9de7c1b..38be93f28a852b3a04894b1d72ae9c9297cb41f3 100644 (file)
--- a/test/CodeGen/PowerPC/split-index-tc.ll
+++ b/test/CodeGen/PowerPC/split-index-tc.ll
@@ -13,7 +13,7 @@ define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align
 ; CHECK-NOT: lhzu
 
 entry:
-  %0 = load %"class.llvm::MachineOperand"** undef, align 8
+  %0 = load %"class.llvm::MachineOperand"*, %"class.llvm::MachineOperand"** undef, align 8
   br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123
 
 cond.false.i123:                                  ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
@@ -22,7 +22,7 @@ cond.false.i123:                                  ; preds = %_ZN4llvm12MachineIn
 _ZNK4llvm14MachineOperand6getRegEv.exit:          ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit
   %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0, i64 undef, i32 1
   %1 = bitcast [3 x i8]* %IsDef.i to i24*
-  %bf.load.i = load i24* %1, align 1
+  %bf.load.i = load i24, i24* %1, align 1
   %2 = and i24 %bf.load.i, 128
   br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph
 
@@ -61,7 +61,7 @@ cond.false.i257:                                  ; preds = %if.end55
   unreachable
 
 _ZNK4llvm14MachineOperand6isDeadEv.exit262:       ; preds = %if.end55
-  %bf.load.i259 = load i24* %1, align 1
+  %bf.load.i259 = load i24, i24* %1, align 1
   br i1 undef, label %if.then57, label %if.else59
 
 if.then57:                                        ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262