AArch64: make inexact signalling on round Darwin-specific

[oota-llvm.git] / test / CodeGen / PowerPC / vec_call.ll

diff --git a/test/CodeGen/PowerPC/vec_call.ll b/test/CodeGen/PowerPC/vec_call.ll
index b2b91fe3f45cfbfb256f5ddc1a13099d267a8403..4511315c3bfade4460c09cce5722349912ae0700 100644 (file)
--- a/test/CodeGen/PowerPC/vec_call.ll
+++ b/test/CodeGen/PowerPC/vec_call.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
 
-<4 x int> %test_arg(<4 x int> %A, <4 x int> %B) {
-        %C = add <4 x int> %A, %B
-        ret <4 x int> %C
+define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) {
+       %C = add <4 x i32> %A, %B               ; <<4 x i32>> [#uses=1]
+       ret <4 x i32> %C
 }
 
-<4 x int> %foo() {
-       %X = call <4 x int> %test_arg(<4 x int> zeroinitializer, <4 x int> zeroinitializer)
-       ret <4 x int> %X
+define <4 x i32> @foo() {
+       %X = call <4 x i32> @test_arg( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )           ; <<4 x i32>> [#uses=1]
+       ret <4 x i32> %X
 }