Enable PPC CTR loop formation by default.

[oota-llvm.git] / test / CodeGen / PowerPC / vec_constants.ll

diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index c4b42b9e9b8acff894ed8fb9fa3bb18cebd52fd4..399f19f8d2e29801ec44e9c8c0971240452d99f3 100644 (file)
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep CPI
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI
 
-define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
+define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
        %tmp = load <4 x i32>* %P1              ; <<4 x i32>> [#uses=1]
        %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 >              ; <<4 x i32>> [#uses=1]
        store <4 x i32> %tmp4, <4 x i32>* %P1
@@ -15,26 +15,30 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
        ret void
 }
 
-define <4 x i32> @test_30() {
+define <4 x i32> @test_30() nounwind {
        ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
 }
 
-define <4 x i32> @test_29() {
+define <4 x i32> @test_29() nounwind {
        ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
 }
 
-define <8 x i16> @test_n30() {
+define <8 x i16> @test_n30() nounwind {
        ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
 }
 
-define <16 x i8> @test_n104() {
+define <16 x i8> @test_n104() nounwind {
        ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
 }
 
-define <4 x i32> @test_vsldoi() {
+define <4 x i32> @test_vsldoi() nounwind {
        ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
 }
 
-define <4 x i32> @test_rol() {
+define <8 x i16> @test_vsldoi_65023() nounwind {
+       ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
+}
+
+define <4 x i32> @test_rol() nounwind {
        ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 }