Specify complete triple for fp128 tests.

[oota-llvm.git] / test / CodeGen / PowerPC / vec_constants.ll

diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index 6b2e6d49ad01fcb48ea5b6ccdf8eb783da056320..399f19f8d2e29801ec44e9c8c0971240452d99f3 100644 (file)
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -1,23 +1,44 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 &&
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep CPI
-
-
-; Tests spltw(0x80000000) and spltw(0x7FFFFFFF).
-void %test1(<4 x int>* %P1, <4 x int>* %P2, <4 x float>* %P3) {
-        %tmp = load <4 x int>* %P1              
-        %tmp4 = and <4 x int> %tmp, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 >                
-        store <4 x int> %tmp4, <4 x int>* %P1
-        %tmp7 = load <4 x int>* %P2             
-        %tmp9 = and <4 x int> %tmp7, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 >           
-        store <4 x int> %tmp9, <4 x int>* %P2
-        %tmp = load <4 x float>* %P3            
-        %tmp11 = cast <4 x float> %tmp to <4 x int>             
-        %tmp12 = and <4 x int> %tmp11, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 >
-        %tmp13 = cast <4 x int> %tmp12 to <4 x float>
-        store <4 x float> %tmp13, <4 x float>* %P3
-        ret void
-}
-
-<4 x int> %test2() {
-        ret <4 x int> <int 30, int 30, int 30, int 30>
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI
+
+define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
+       %tmp = load <4 x i32>* %P1              ; <<4 x i32>> [#uses=1]
+       %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 >              ; <<4 x i32>> [#uses=1]
+       store <4 x i32> %tmp4, <4 x i32>* %P1
+       %tmp7 = load <4 x i32>* %P2             ; <<4 x i32>> [#uses=1]
+       %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 >         ; <<4 x i32>> [#uses=1]
+       store <4 x i32> %tmp9, <4 x i32>* %P2
+       %tmp.upgrd.1 = load <4 x float>* %P3            ; <<4 x float>> [#uses=1]
+       %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+       %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 >               ; <<4 x i32>> [#uses=1]
+       %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float>                ; <<4 x float>> [#uses=1]
+       store <4 x float> %tmp13, <4 x float>* %P3
+       ret void
+}
+
+define <4 x i32> @test_30() nounwind {
+       ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
+}
+
+define <4 x i32> @test_29() nounwind {
+       ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
+}
+
+define <8 x i16> @test_n30() nounwind {
+       ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
+}
+
+define <16 x i8> @test_n104() nounwind {
+       ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
+}
+
+define <4 x i32> @test_vsldoi() nounwind {
+       ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
+}
+
+define <8 x i16> @test_vsldoi_65023() nounwind {
+       ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
+}
+
+define <4 x i32> @test_rol() nounwind {
+       ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 }