%c = sext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
-; CHECK: v16si8_sext_in_reg:
+; CHECK-LABEL: v16si8_sext_in_reg:
; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
%c = zext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
-; CHECK: v16si8_zext_in_reg:
+; CHECK-LABEL: v16si8_zext_in_reg:
; CHECK: vspltisb [[VMASK:[0-9]+]], 15
; CHECK-NEXT: vand 2, 2, [[VMASK]]
%c = sext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
-; CHECK: v8si16_sext_in_reg:
+; CHECK-LABEL: v8si16_sext_in_reg:
; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
%c = zext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
-; CHECK: v8si16_zext_in_reg:
+; CHECK-LABEL: v8si16_zext_in_reg:
; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]
%c = sext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
-; CHECK: v4si32_sext_in_reg:
+; CHECK-LABEL: v4si32_sext_in_reg:
; CHECK: vslw
; CHECK: vsraw
; CHECK: blr
%c = zext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
-; CHECK: v4si32_zext_in_reg:
+; CHECK-LABEL: v4si32_zext_in_reg:
; CHECK: vspltisw [[VMASK:[0-9]+]], -16
; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]