[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / vec_mul.ll

diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll
index dee03693fc8f04a4244b4fa72a7e9a6d4627313b..e1c9217ff135a901770e18f4ca8e04bcf6986216 100644 (file)
--- a/test/CodeGen/PowerPC/vec_mul.ll
+++ b/test/CodeGen/PowerPC/vec_mul.ll
@@ -1,13 +1,12 @@
-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s -check-prefix=CHECK-LE
-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-LE-VSX
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx -mattr=-power8-altivec | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE-VSX
 
 define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
-       %tmp = load <4 x i32>* %X               ; <<4 x i32>> [#uses=1]
-       %tmp2 = load <4 x i32>* %Y              ; <<4 x i32>> [#uses=1]
+       %tmp = load <4 x i32>, <4 x i32>* %X            ; <<4 x i32>> [#uses=1]
+       %tmp2 = load <4 x i32>, <4 x i32>* %Y           ; <<4 x i32>> [#uses=1]
        %tmp3 = mul <4 x i32> %tmp, %tmp2               ; <<4 x i32>> [#uses=1]
        ret <4 x i32> %tmp3
 }
@@ -25,8 +24,8 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
 ; CHECK-LE-VSX-NOT: mullw
 
 define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
-       %tmp = load <8 x i16>* %X               ; <<8 x i16>> [#uses=1]
-       %tmp2 = load <8 x i16>* %Y              ; <<8 x i16>> [#uses=1]
+       %tmp = load <8 x i16>, <8 x i16>* %X            ; <<8 x i16>> [#uses=1]
+       %tmp2 = load <8 x i16>, <8 x i16>* %Y           ; <<8 x i16>> [#uses=1]
        %tmp3 = mul <8 x i16> %tmp, %tmp2               ; <<8 x i16>> [#uses=1]
        ret <8 x i16> %tmp3
 }
@@ -44,8 +43,8 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
 ; CHECK-LE-VSX-NOT: mullw
 
 define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
-       %tmp = load <16 x i8>* %X               ; <<16 x i8>> [#uses=1]
-       %tmp2 = load <16 x i8>* %Y              ; <<16 x i8>> [#uses=1]
+       %tmp = load <16 x i8>, <16 x i8>* %X            ; <<16 x i8>> [#uses=1]
+       %tmp2 = load <16 x i8>, <16 x i8>* %Y           ; <<16 x i8>> [#uses=1]
        %tmp3 = mul <16 x i8> %tmp, %tmp2               ; <<16 x i8>> [#uses=1]
        ret <16 x i8> %tmp3
 }
@@ -69,8 +68,8 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
 ; CHECK-LE-VSX-NOT: mullw
 
 define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
-       %tmp = load <4 x float>* %X
-       %tmp2 = load <4 x float>* %Y
+       %tmp = load <4 x float>, <4 x float>* %X
+       %tmp2 = load <4 x float>, <4 x float>* %Y
        %tmp3 = fmul <4 x float> %tmp, %tmp2
        ret <4 x float> %tmp3
 }