[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / PowerPC / vec_zero.ll

diff --git a/test/CodeGen/PowerPC/vec_zero.ll b/test/CodeGen/PowerPC/vec_zero.ll
index 8d06a7d94dac1b678e5dff1b0d4b8a53f630cbfc..aec61fbd6bd679ae66b13e51a6181efb226d0d7c 100644 (file)
--- a/test/CodeGen/PowerPC/vec_zero.ll
+++ b/test/CodeGen/PowerPC/vec_zero.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vxor
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vxor
 
 define void @foo(<4 x float>* %P) {
-        %T = load <4 x float>* %P               ; <<4 x float>> [#uses=1]
-        %S = add <4 x float> zeroinitializer, %T                ; <<4 x float>> [#uses=1]
+        %T = load <4 x float>, <4 x float>* %P               ; <<4 x float>> [#uses=1]
+        %S = fadd <4 x float> zeroinitializer, %T                ; <<4 x float>> [#uses=1]
         store <4 x float> %S, <4 x float>* %P
         ret void
 }