[Sparc] Fix an assertion failure while lowering fcmp on long double.

[oota-llvm.git] / test / CodeGen / SPARC / 64cond.ll

diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll
index 694909f9e7283fbc7160c052c30c232a5bce61ff..bdc5e70a2de848a36a2ed0c222239d91ded32df3 100644 (file)
--- a/test/CodeGen/SPARC/64cond.ll
+++ b/test/CodeGen/SPARC/64cond.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=sparcv9 | FileCheck %s
-; Testing 64-bit conditionals.
+; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
+; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
 
 ; CHECK: cmpri
-; CHECK: subcc %i1, 1
-; CHECK: bpe %xcc,
+; CHECK: cmp %i1, 1
+; CHECK: be %xcc,
 define void @cmpri(i64* %p, i64 %x) {
 entry:
   %tobool = icmp eq i64 %x, 1
@@ -18,8 +18,8 @@ if.end:
 }
 
 ; CHECK: cmprr
-; CHECK: subcc %i1, %i2
-; CHECK: bpgu %xcc,
+; CHECK: cmp %i1, %i2
+; CHECK: bgu %xcc,
 define void @cmprr(i64* %p, i64 %x, i64 %y) {
 entry:
   %tobool = icmp ugt i64 %x, %y
@@ -32,3 +32,80 @@ if.then:
 if.end:
   ret void
 }
+
+; CHECK: selecti32_xcc
+; CHECK: cmp %i0, %i1
+; CHECK: movg %xcc, %i2, %i3
+; CHECK: restore %g0, %i3, %o0
+define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
+entry:
+  %tobool = icmp sgt i64 %x, %y
+  %rv = select i1 %tobool, i32 %a, i32 %b
+  ret i32 %rv
+}
+
+; CHECK: selecti64_xcc
+; CHECK: cmp %i0, %i1
+; CHECK: movg %xcc, %i2, %i3
+; CHECK: restore %g0, %i3, %o0
+define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
+entry:
+  %tobool = icmp sgt i64 %x, %y
+  %rv = select i1 %tobool, i64 %a, i64 %b
+  ret i64 %rv
+}
+
+; CHECK: selecti64_icc
+; CHECK: cmp %i0, %i1
+; CHECK: movg %icc, %i2, %i3
+; CHECK: restore %g0, %i3, %o0
+define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
+entry:
+  %tobool = icmp sgt i32 %x, %y
+  %rv = select i1 %tobool, i64 %a, i64 %b
+  ret i64 %rv
+}
+
+; CHECK: selecti64_fcc
+; CHECK: fcmps %f1, %f3
+; CHECK: movul %fcc0, %i2, %i3
+; CHECK: restore %g0, %i3, %o0
+define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
+entry:
+  %tobool = fcmp ult float %x, %y
+  %rv = select i1 %tobool, i64 %a, i64 %b
+  ret i64 %rv
+}
+
+; CHECK: selectf32_xcc
+; CHECK: cmp %i0, %i1
+; CHECK: fmovsg %xcc, %f5, %f7
+; CHECK: fmovs %f7, %f1
+define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
+entry:
+  %tobool = icmp sgt i64 %x, %y
+  %rv = select i1 %tobool, float %a, float %b
+  ret float %rv
+}
+
+; CHECK: selectf64_xcc
+; CHECK: cmp %i0, %i1
+; CHECK: fmovdg %xcc, %f4, %f6
+; CHECK: fmovd %f6, %f0
+define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
+entry:
+  %tobool = icmp sgt i64 %x, %y
+  %rv = select i1 %tobool, double %a, double %b
+  ret double %rv
+}
+
+; The MOVXCC instruction can't use %g0 for its tied operand.
+; CHECK: select_consti64_xcc
+; CHECK: cmp
+; CHECK: movg %xcc, 123, %i{{[0-2]}}
+define i64 @select_consti64_xcc(i64 %x, i64 %y) {
+entry:
+  %tobool = icmp sgt i64 %x, %y
+  %rv = select i1 %tobool, i64 123, i64 0
+  ret i64 %rv
+}