; CHECK: cmpri
; CHECK: cmp %i1, 1
-; CHECK: bpe %xcc,
+; CHECK: be %xcc,
define void @cmpri(i64* %p, i64 %x) {
entry:
%tobool = icmp eq i64 %x, 1
; CHECK: cmprr
; CHECK: cmp %i1, %i2
-; CHECK: bpgu %xcc,
+; CHECK: bgu %xcc,
define void @cmprr(i64* %p, i64 %x, i64 %y) {
entry:
%tobool = icmp ugt i64 %x, %y
; CHECK: selectf32_xcc
; CHECK: cmp %i0, %i1
; CHECK: fmovsg %xcc, %f5, %f7
-; CHECK: fmovs %f7, %f1
+; CHECK: fmovs %f7, %f0
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
entry:
%tobool = icmp sgt i64 %x, %y
; The MOVXCC instruction can't use %g0 for its tied operand.
; CHECK: select_consti64_xcc
; CHECK: cmp
-; CHECK: movg %xcc, 123, %i0
+; CHECK: movg %xcc, 123, %i{{[0-2]}}
define i64 @select_consti64_xcc(i64 %x, i64 %y) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i64 123, i64 0
ret i64 %rv
}
+
+; CHECK-LABEL: setcc_resultty
+; CHECK-DAG: srax %i0, 63, %o0
+; CHECK-DAG: mov %i0, %o1
+; CHECK-DAG: mov 0, %o2
+; CHECK-DAG: mov 32, %o3
+; CHECK-DAG: call __multi3
+; CHECK: cmp
+; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]]
+; CHECK: or [[R]], %i1, %i0
+
+define i1 @setcc_resultty(i64 %a, i1 %b) {
+ %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
+ %a1 = extractvalue { i64, i1 } %a0, 1
+ %a4 = or i1 %a1, %b
+ ret i1 %a4
+}
+
+declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)