[x32] Fix FrameIndex check in SelectLEA64_32Addr

[oota-llvm.git] / test / CodeGen / SystemZ / cond-store-04.ll

diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll
index 22f5fd4226514753206f97c207da5c4e25af3a1a..346b51a17d78f4901192332422afaf44d6244964 100644 (file)
--- a/test/CodeGen/SystemZ/cond-store-04.ll
+++ b/test/CodeGen/SystemZ/cond-store-04.ll
@@ -1,19 +1,19 @@
 ; Test 64-bit conditional stores that are presented as selects.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i64 *)
 
 ; Test with the loaded value first.
 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -22,14 +22,14 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %alt, i64 %orig
   store i64 %res, i64 *%ptr
@@ -38,7 +38,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STG range.
 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -46,7 +46,7 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65535
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -56,7 +56,7 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -65,7 +65,7 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65536
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -74,7 +74,7 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -82,7 +82,7 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65536
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -92,7 +92,7 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -101,7 +101,7 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65537
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -110,7 +110,7 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 
 ; Check that STG allows an index.
 define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -120,7 +120,7 @@ define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -129,13 +129,13 @@ define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
 ; CHECK: stg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load volatile i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -144,13 +144,13 @@ define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK-LABEL: f9:
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store volatile i64 %res, i64 *%ptr
@@ -163,13 +163,13 @@ define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CSG.
-; CHECK: f10:
-; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
+; CHECK-LABEL: f10:
+; CHECK: lg {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
 ; CHECK: stg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load atomic i64 *%ptr unordered, align 8
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
@@ -179,13 +179,13 @@ define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CSG.
-; CHECK: f11:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK-LABEL: f11:
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
-; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2)
+; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store atomic i64 %res, i64 *%ptr unordered, align 8
@@ -194,7 +194,7 @@ define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(i64 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
@@ -205,7 +205,7 @@ define void @f12(i64 %alt, i32 %limit) {
 ; CHECK: br %r14
   %ptr = alloca i64
   call void @foo(i64 *%ptr)
-  %cond = icmp ult i32 %limit, 42
+  %cond = icmp ult i32 %limit, 420
   %orig = load i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr