; CHECK-NEXT: jl
; CHECK: br %r14
entry:
- %val = load i16 *@g
+ %val = load i16 , i16 *@g
%src2 = zext i16 %val to i32
%cond = icmp ult i32 %src1, %src2
br i1 %cond, label %exit, label %mulb
; CHECK-NOT: clhrl
; CHECK: br %r14
entry:
- %val = load i16 *@g
+ %val = load i16 , i16 *@g
%src2 = zext i16 %val to i32
%cond = icmp slt i32 %src1, %src2
br i1 %cond, label %exit, label %mulb
; CHECK-NEXT: je
; CHECK: br %r14
entry:
- %val = load i16 *@g
+ %val = load i16 , i16 *@g
%src2 = zext i16 %val to i32
%cond = icmp eq i32 %src1, %src2
br i1 %cond, label %exit, label %mulb
; CHECK-NEXT: jlh
; CHECK: br %r14
entry:
- %val = load i16 *@g
+ %val = load i16 , i16 *@g
%src2 = zext i16 %val to i32
%cond = icmp ne i32 %src1, %src2
br i1 %cond, label %exit, label %mulb
; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
-; CHECK: clr %r2, [[VAL]]
-; CHECK-NEXT: jl
+; CHECK: clrjl %r2, [[VAL]],
; CHECK: br %r14
entry:
- %val = load i16 *@h, align 1
+ %val = load i16 , i16 *@h, align 1
%src2 = zext i16 %val to i32
%cond = icmp ult i32 %src1, %src2
br i1 %cond, label %exit, label %mulb
%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
ret i32 %res
}
+
+; Check the comparison can be reversed if that allows CLHRL to be used.
+define i32 @f6(i32 %src2) {
+; CHECK-LABEL: f6:
+; CHECK: clhrl %r2, g
+; CHECK-NEXT: jh {{\.L.*}}
+; CHECK: br %r14
+entry:
+ %val = load i16 , i16 *@g
+ %src1 = zext i16 %val to i32
+ %cond = icmp ult i32 %src1, %src2
+ br i1 %cond, label %exit, label %mulb
+mulb:
+ %mul = mul i32 %src2, %src2
+ br label %exit
+exit:
+ %res = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
+ ret i32 %res
+}