aad/fix labels in test/CodeGen/X86/StackColoring.ll

[oota-llvm.git] / test / CodeGen / SystemZ / int-conv-04.ll

diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll
index c3d445a57563a0a49e2721072991794c88d2f230..a0f5d63d2605e5f461eaeb9aa55cb040dc0b8f3a 100644 (file)
--- a/test/CodeGen/SystemZ/int-conv-04.ll
+++ b/test/CodeGen/SystemZ/int-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 255
@@ -33,21 +33,21 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGC with no displacement.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
-  %byte = load i8 *%src
+  %byte = load i8 , i8 *%src
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
 
 ; Check the high end of the LLGC range.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgc %r2, 524287(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524287
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524287
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -55,34 +55,34 @@ define i64 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 524288
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
 
 ; Check the high end of the negative LLGC range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgc %r2, -1(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -1
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -1
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
 
 ; Check the low end of the LLGC range.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgc %r2, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524288
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524288
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -90,25 +90,25 @@ define i64 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i8 *%src, i64 -524289
-  %byte = load i8 *%ptr
+  %ptr = getelementptr i8, i8 *%src, i64 -524289
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
 
 ; Check that LLGC allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i8 *
-  %byte = load i8 *%ptr
+  %byte = load i8 , i8 *%ptr
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
@@ -116,25 +116,25 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGCR.  We want
 ; to use LLGC if possible.
 define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
-  %val0 = load volatile i64 *%ptr
-  %val1 = load volatile i64 *%ptr
-  %val2 = load volatile i64 *%ptr
-  %val3 = load volatile i64 *%ptr
-  %val4 = load volatile i64 *%ptr
-  %val5 = load volatile i64 *%ptr
-  %val6 = load volatile i64 *%ptr
-  %val7 = load volatile i64 *%ptr
-  %val8 = load volatile i64 *%ptr
-  %val9 = load volatile i64 *%ptr
-  %val10 = load volatile i64 *%ptr
-  %val11 = load volatile i64 *%ptr
-  %val12 = load volatile i64 *%ptr
-  %val13 = load volatile i64 *%ptr
-  %val14 = load volatile i64 *%ptr
-  %val15 = load volatile i64 *%ptr
+  %val0 = load volatile i64 , i64 *%ptr
+  %val1 = load volatile i64 , i64 *%ptr
+  %val2 = load volatile i64 , i64 *%ptr
+  %val3 = load volatile i64 , i64 *%ptr
+  %val4 = load volatile i64 , i64 *%ptr
+  %val5 = load volatile i64 , i64 *%ptr
+  %val6 = load volatile i64 , i64 *%ptr
+  %val7 = load volatile i64 , i64 *%ptr
+  %val8 = load volatile i64 , i64 *%ptr
+  %val9 = load volatile i64 , i64 *%ptr
+  %val10 = load volatile i64 , i64 *%ptr
+  %val11 = load volatile i64 , i64 *%ptr
+  %val12 = load volatile i64 , i64 *%ptr
+  %val13 = load volatile i64 , i64 *%ptr
+  %val14 = load volatile i64 , i64 *%ptr
+  %val15 = load volatile i64 , i64 *%ptr
 
   %trunc0 = trunc i64 %val0 to i8
   %trunc1 = trunc i64 %val1 to i8