; Test register extension, starting with an i32.
define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%half = trunc i32 %a to i16
; ...and again with an i64.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%half = trunc i64 %a to i16
; Check ANDs that are equivalent to zero extension.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%ext = and i64 %a, 65535
; Check LLGH with no displacement.
define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgh %r2, 0(%r2)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the LLGH range.
define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llgh %r2, 524286(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: llgh %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LLGH range.
define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llgh %r2, -2(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the LLGH range.
define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llgh %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524290
; CHECK: llgh %r2, 0(%r2)
; CHECK: br %r14
; Check that LLGH allows an index
define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llgh %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LLGHR. We want
; to use LLGH if possible.
define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr