[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / Thumb / pop.ll

diff --git a/test/CodeGen/Thumb/pop.ll b/test/CodeGen/Thumb/pop.ll
index c5e86ad45bc31291aff3e1e4b680e0138b4336b4..851f793e5ee07e458736407c0360ad58a69667b2 100644 (file)
--- a/test/CodeGen/Thumb/pop.ll
+++ b/test/CodeGen/Thumb/pop.ll
@@ -1,13 +1,15 @@
 ; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
 ; rdar://7268481
 
-define arm_apcscc void @t(i8* %a, ...) nounwind {
-; CHECK:      t:
-; CHECK:      pop {r3}
-; CHECK-NEXT: add sp, #3 * 4
-; CHECK-NEXT: bx r3
+define void @t(i8* %a, ...) nounwind {
+; CHECK-LABEL:      t:
+; CHECK:      pop {[[POP_REG:r[0-3]]]}
+; CHECK-NEXT: add sp, #12
+; CHECK-NEXT: bx [[POP_REG]]
 entry:
-  %a.addr = alloca i8*
-  store i8* %a, i8** %a.addr
+  %a.addr = alloca i8, i32 4
+  call void @llvm.va_start(i8* %a.addr)
   ret void
 }
+
+declare void @llvm.va_start(i8*) nounwind