[Hexagon] Fixing load instruction parsing and reenabling tests.

[oota-llvm.git] / test / CodeGen / Thumb / rev.ll

diff --git a/test/CodeGen/Thumb/rev.ll b/test/CodeGen/Thumb/rev.ll
index 5e163f8f96bce5751de2117d68dade1463c51aef..3e947022e601823f479e52360feb8116789f6c63 100644 (file)
--- a/test/CodeGen/Thumb/rev.ll
+++ b/test/CodeGen/Thumb/rev.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s
+; RUN: llc -mtriple=thumb-eabi -mattr=+v6 %s -o - | FileCheck %s
 
 define i32 @test1(i32 %X) nounwind {
 ; CHECK: test1
@@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind {
 ; rdar://9147637
 define i32 @test3(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: revsh r0, r0
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   %1 = sext i16 %0 to i32
@@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone
 
 define i32 @test4(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: revsh r0, r0
   %conv = zext i16 %a to i32
   %shr9 = lshr i16 %a, 8