ARM: When spilling extra registers for alignment, prefer low registers on all Thumb...

[oota-llvm.git] / test / CodeGen / Thumb2 / 2009-08-06-SpDecBug.ll

diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
index 40775358a944df3e5fe9e9657c879698bde5a866..a451321838e7c8e103788234e73b737a55566418 100644 (file)
--- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -1,13 +1,19 @@
-; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -arm-atomic-cfg-tidy=0 | FileCheck %s
 ; PR4659
 ; PR4682
 
-define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
+define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
 entry:
-; CHECK: __gcov_execlp:
-; CHECK: mov sp, r7
-; CHECK: sub sp, #4
-       call arm_aapcscc  void @__gcov_flush() nounwind
+; CHECK-LABEL: __gcov_execlp:
+; CHECK: sub sp, #8
+; CHECK: push
+; CHECK: add r7, sp, #8
+; CHECK: sub.w r4, r7, #8
+; CHECK: mov sp, r4
+; CHECK-NOT: mov sp, r7
+; CHECK: add sp, #8
+       call void @__gcov_flush() nounwind
+       call void @llvm.va_start(i8* null)
        br i1 undef, label %bb5, label %bb
 
 bb:            ; preds = %bb, %entry
@@ -15,10 +21,12 @@ bb:         ; preds = %bb, %entry
 
 bb5:           ; preds = %bb, %entry
        %0 = alloca i8*, i32 undef, align 4             ; <i8**> [#uses=1]
-       %1 = call arm_aapcscc  i32 @execvp(i8* %path, i8** %0) nounwind         ; <i32> [#uses=1]
+       %1 = call i32 @execvp(i8* %path, i8** %0) nounwind              ; <i32> [#uses=1]
        ret i32 %1
 }
 
-declare hidden arm_aapcscc void @__gcov_flush()
+declare hidden void @__gcov_flush()
 
-declare arm_aapcscc i32 @execvp(i8*, i8**) nounwind
+declare i32 @execvp(i8*, i8**) nounwind
+
+declare void @llvm.va_start(i8*) nounwind