Fix PR18572 - llc crash during GenericScheduler::initPolicy().

[oota-llvm.git] / test / CodeGen / Thumb2 / 2013-03-06-vector-sext-operand-scalarize.ll

diff --git a/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll b/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
index 203815fadc9cdfbb7194fe3972cbca33aaad75e4..974fade64f0b8df2de35c964848ed59f17b68eef 100644 (file)
--- a/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
+++ b/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
@@ -3,7 +3,7 @@
 ; Testing that these don't crash/assert. The loop vectorizer can end up
 ; with odd constructs like this. The code actually generated is incidental.
 define <1 x i64> @test_zext(i32 %a) nounwind {
-; CHECK: test_zext:
+; CHECK-LABEL: test_zext:
   %Cmp = icmp uge i32 %a, 42
   %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
   %Se = zext <1 x i1> %vec to <1 x i64>
@@ -11,7 +11,7 @@ define <1 x i64> @test_zext(i32 %a) nounwind {
 }
 
 define <1 x i64> @test_sext(i32 %a) nounwind {
-; CHECK: test_sext:
+; CHECK-LABEL: test_sext:
   %Cmp = icmp uge i32 %a, 42
   %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
   %Se = sext <1 x i1> %vec to <1 x i64>