Add support for v1i128 type.

[oota-llvm.git] / test / CodeGen / Thumb2 / thumb2-rsb.ll

diff --git a/test/CodeGen/Thumb2/thumb2-rsb.ll b/test/CodeGen/Thumb2/thumb2-rsb.ll
index 934e37713d710b62e883ba7195dc4cab47f14aa4..1c5acadcf40ed16b49030c8ad58f2d0706c7d655 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-rsb.ll
+++ b/test/CodeGen/Thumb2/thumb2-rsb.ll
@@ -1,9 +1,35 @@
-; XFAIL: *
-; this will match as "sub" until we get register shifting
-
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]*} | count 1
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-    %tmp = sub i32 %b, %a
-    ret i32 %tmp
+    %tmp = shl i32 %b, 5
+    %tmp1 = sub i32 %tmp, %a
+    ret i32 %tmp1
+}
+; CHECK-LABEL: f1:
+; CHECK:       rsb     r0, r0, r1, lsl #5
+
+define i32 @f2(i32 %a, i32 %b) {
+    %tmp = lshr i32 %b, 6
+    %tmp1 = sub i32 %tmp, %a
+    ret i32 %tmp1
+}
+; CHECK-LABEL: f2:
+; CHECK:       rsb     r0, r0, r1, lsr #6
+
+define i32 @f3(i32 %a, i32 %b) {
+    %tmp = ashr i32 %b, 7
+    %tmp1 = sub i32 %tmp, %a
+    ret i32 %tmp1
+}
+; CHECK-LABEL: f3:
+; CHECK:       rsb     r0, r0, r1, asr #7
+
+define i32 @f4(i32 %a, i32 %b) {
+    %l8 = shl i32 %a, 24
+    %r8 = lshr i32 %a, 8
+    %tmp = or i32 %l8, %r8
+    %tmp1 = sub i32 %tmp, %a
+    ret i32 %tmp1
 }
+; CHECK-LABEL: f4:
+; CHECK:       rsb     r0, r0, r0, ror #8