[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing...

[oota-llvm.git] / test / CodeGen / WebAssembly / func.ll

diff --git a/test/CodeGen/WebAssembly/func.ll b/test/CodeGen/WebAssembly/func.ll
index 5d84392fc4434c924d72031e68aea43604c2c809..cd78df0d1a2cfe2be9c664a3a4aaa5ca04cc1b9c 100644 (file)
--- a/test/CodeGen/WebAssembly/func.ll
+++ b/test/CodeGen/WebAssembly/func.ll
@@ -5,35 +5,43 @@
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-; CHECK-LABEL: (func $f0{{$}}
-; CHECK: (return){{$}}
-; CHECK-NEXT: ) ;; end func $f0{{$}}
+; CHECK-LABEL: f0:
+; CHECK: return{{$}}
+; CHECK: .size f0,
 define void @f0() {
   ret void
 }
 
-; CHECK-LABEL: (func $f1{{$}}
-; CHECK-NEXT: (result i32){{$}}
-; CHECK-NEXT: (set_local @0 (immediate 0)){{$}}
-; CHECK-NEXT: (return @0){{$}}
-; CHECK-NEXT: ) ;; end func $f1{{$}}
+; CHECK-LABEL: f1:
+; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .local i32{{$}}
+; CHECK-NEXT: i32.const push, 0{{$}}
+; CHECK-NEXT: set_local 0, pop{{$}}
+; CHECK-NEXT: return (get_local 0){{$}}
+; CHECK: .size f1,
 define i32 @f1() {
   ret i32 0
 }
 
-; CHECK-LABEL: (func $f2{{$}}
-; CHECK-NEXT: (param i32) (param f32) (result i32){{$}}
-; CHECK-NEXT: (set_local @0 (immediate 0)){{$}}
-; CHECK-NEXT: (return @0){{$}}
-; CHECK-NEXT: ) ;; end func $f2{{$}}
+; CHECK-LABEL: f2:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .param f32{{$}}
+; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: .local i32{{$}}
+; CHECK-NEXT: i32.const push, 0{{$}}
+; CHECK-NEXT: set_local 2, pop{{$}}
+; CHECK-NEXT: return (get_local 2){{$}}
+; CHECK: .size f2,
 define i32 @f2(i32 %p1, float %p2) {
   ret i32 0
 }
 
-; CHECK-LABEL: (func $f3{{$}}
-; CHECK-NEXT: (param i32) (param f32){{$}}
-; CHECK-NEXT: (return){{$}}
-; CHECK-NEXT: ) ;; end func $f3{{$}}
+; CHECK-LABEL: f3:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .param f32{{$}}
+; CHECK-NOT: .local
+; CHECK-NEXT: return{{$}}
+; CHECK: .size f3,
 define void @f3(i32 %p1, float %p2) {
   ret void
 }