[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing...

[oota-llvm.git] / test / CodeGen / WebAssembly / func.ll

diff --git a/test/CodeGen/WebAssembly/func.ll b/test/CodeGen/WebAssembly/func.ll
index 7d16fd38c8a4f6b13633bbd7a7dad8dd319bd3bf..cd78df0d1a2cfe2be9c664a3a4aaa5ca04cc1b9c 100644 (file)
--- a/test/CodeGen/WebAssembly/func.ll
+++ b/test/CodeGen/WebAssembly/func.ll
@@ -15,9 +15,9 @@ define void @f0() {
 ; CHECK-LABEL: f1:
 ; CHECK-NEXT: .result i32{{$}}
 ; CHECK-NEXT: .local i32{{$}}
-; CHECK-NEXT: i32.const 0{{$}}
+; CHECK-NEXT: i32.const push, 0{{$}}
 ; CHECK-NEXT: set_local 0, pop{{$}}
-; CHECK-NEXT: i32.return (get_local 0){{$}}
+; CHECK-NEXT: return (get_local 0){{$}}
 ; CHECK: .size f1,
 define i32 @f1() {
   ret i32 0
@@ -28,9 +28,9 @@ define i32 @f1() {
 ; CHECK-NEXT: .param f32{{$}}
 ; CHECK-NEXT: .result i32{{$}}
 ; CHECK-NEXT: .local i32{{$}}
-; CHECK-NEXT: i32.const 0{{$}}
+; CHECK-NEXT: i32.const push, 0{{$}}
 ; CHECK-NEXT: set_local 2, pop{{$}}
-; CHECK-NEXT: i32.return (get_local 2){{$}}
+; CHECK-NEXT: return (get_local 2){{$}}
 ; CHECK: .size f2,
 define i32 @f2(i32 %p1, float %p2) {
   ret i32 0
@@ -40,7 +40,7 @@ define i32 @f2(i32 %p1, float %p2) {
 ; CHECK-NEXT: .param i32{{$}}
 ; CHECK-NEXT: .param f32{{$}}
 ; CHECK-NOT: .local
-; CHECK-NEXT: void.return{{$}}
+; CHECK-NEXT: return{{$}}
 ; CHECK: .size f3,
 define void @f3(i32 %p1, float %p2) {
   ret void